Negative Bias Temperature Instability Research Articles

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10[Formula: see text]nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48[Formula: see text]nW and a delay of 9.16[Formula: see text]ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

A comprehensive study of negative bias temperature instability in MOS structures

We propose systematic experiments of Negative Bias Temperature Instability and a model of the threshold voltage during and after the stress. The stress conditions were varied as function of time, voltage, temperature. After the stress end, recovery was monitored for ten seconds. The model takes into account the activity of interface, bulk and border traps, clarifies each contribution during and after the stress and the hydrogen related mechanism. The fast release kinetics of border traps after the stress end is discussed, the entity of the threshold voltage recovery before measurement is calculated and its possible impact on the overall reliability assessment is discussed.

Aging-Aware Critical Path Selection via Graph Attention Networks

In advanced technology nodes, aging effects like negative and positive bias temperature instability (NBTI and PBTI) become increasingly significant, making timing closure and optimization more challenging. Unfortunately, conventional critical path selection tools used in reliability-aware design flow cannot accurately identify critical paths under different aging conditions. To address this issue, we propose an aging-aware critical path selection flow comprising two parts: critical cell detection and path criticality computation. We employ graph-attention networks (GATs) to predict the critical cells in the aged circuits, and a path criticality computation algorithm that takes into account circuit-level and transistor-level parameters to generate path criticality rank lists. Our experimental results demonstrate that our GAT model outperforms classical machine learning models in detecting critical cells. Additionally, compared with the commercial tool, our aging-aware flow achieves an average accuracy of 99.52%, 98.69%, and 97.20% for top-10%, top-5%, and top-1% path sets respectively, in five industrial designs subjected to different aging conditions and workloads.

A modelling method of the on-state resistance of p-channel power MOSFETs under NBTI stress

Negative Bias Temperature Instability (NBTI) of p-channel power MOSFETs is a primary concern in gate oxide degradation. Instead of a qualitative conclusion, predicting the degradation in the on-state resistance during long-term operation is significant. This paper evaluates the degradation of each component of the on-state resistance under NBTI stress. By dividing the on-state resistance into two parts based on whether it is affected by NBTI, we obtain a first-order linear model form to model the on-state resistance. This study can support the physical modelling and the remaining useful life prediction of the on-state resistance in long-term operation.

Time-dependent statistical NBTI model for aging assessment in circuit level implemented with open model interface

As technology nodes continue to shrink, the impact of aging problems on devices has become increasingly important. One significant aging problem that affects device characteristics and circuit performance is Negative Bias Temperature Instability (NBTI). Under small-size conditions, fluctuations in device parameters such as threshold voltage due to aging are not negligible. To capture these fluctuations, an improved statistical model has been proposed. The time-dependent statistical model accounts for the average change in the number of charged defects due to NBTI and enables the evaluation of degradation fluctuations over time. The model prediction of the threshold voltage degradation of devices in advanced technology is verified with different measured data. Furthermore, the model is implemented with the Open Model Interface (OMI) for the circuit-level degradation simulation, taking advantage of OMI's convenience and compatibility with different circuit simulators. The integration of the proposed model into the OMI benefits in predicting the degradations difference among the transistors in the circuits, reducing the overestimation of aging degradation compared to the methods that assume every transistor experiences the same and worst degradation.

A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit

NBTI is a key reliability challenge in nanoscale digital design, and it is vital to address it throughout the exploration of design space at high levels of abstraction in order to improve reliability. A prediction model of aging that is adequate for these levels ought to be faster. In addition to this, the model should be able to forecast the recently discovered stochastic consequences of growing older. The purpose of this study is to offer a model that is based on machine learning (ML) and can predict aging effects. After obtaining a training set of sufficient size using Synopsis HSPICE (MOSFET Reliability, MOSRA) in the beginning, the machine-learning-based model is then trained and built in order to forecast the aging statistical features. Evaluation is done on a number of machine learning techniques, including Adaptive Neuro-Fuzzy Inference System (ANFIS), K-Nearest Neighbor (KNN), Support Vector Machine (SVM) and Random Forest (RF). The findings indicate that ANFIS algorithms are very effective in the process of age prediction. The proposed technique shows that the aging prediction runtime is reduced by more than 99% when compared to the MOSRA-based approach, and accurate predictions of the statistical properties of aging are obtained with an accuracy of more than 99% on complementary metal oxide semiconductor (CMOS) and metal gate/high-K (MGK) circuits at the 22nm technology node.

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs.

We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.

Research on reliability of complementary metal oxide semiconductor integrated circuit

Complementary metal oxide semiconductor (CMOS) devices are an important part of integrated circuit (IC), but in the application process, it has many reliability problems, such as negative-bias temperature instability (NBTI), electromigration (EM), time-dependent gate oxide breakdown (TDDB), hot carrier injection (HCI), etc. These reliability problems can affect the threshold voltage and mobility of the device. In order to improve the reliability of integrated circuits, these reliability problems are systematically studied in this paper.

Modeling of negative bias temperature instability

Negative bias temperature instability is regarded as one of the most important reliability concerns of highly scaled PMOS transistors. As a consequence of the continuous downscaling of semiconductor devices this issue has become even more important over the last couple of years due to the high electric fields in the oxide and the routine incorporation of nitrogen. During negative bias temperature stress a shift in important parameters of PMOS transistors, such as the threshold voltage, subthreshold slope, and mobility is observed. Modeling efforts date back to the reaction-diffusion model proposed by Jeppson and Svensson thirty years ago which has been continuously refined since then. Although the reaction-diffusion model is able to explain many experimentally observed characteristics, some microscopic details are still not well understood. Recently, various alternative explanations have been put forward, some of them extending, some of them contradicting the standard reaction-diffusion model. We review these explanations with a special focus on modeling issues.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability (NBTI) can be attributed to three mutually uncoupled physical mechanisms, i.e., the generation of interface traps (ΔV IT), hole trapping in pre-existing gate oxide defects (ΔV HT), and the generation of gate oxide defects (ΔV OT). In this work, the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate (HKMG) process is thoroughly studied. The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature. The effects of the three underlying subcomponents are evaluated by using the comprehensive models. It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress. Moreover, the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted. The dependence of operating lifetime on stress bias and temperature is also discussed. It is observed that NBTI lifetime significantly decreases as the stress increases. Furthermore, the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

On the Understanding of Defects in Short-Term Negative Bias Temperature Instability (NBTI) for Sub-20-nm DRAM Technology

Short-term Negative Bias Temperature Instability (NBTI) was investigated in sub-20-nm DRAM technology. By using Variable T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">charge</sub> -T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">discharge</sub> Amplitude Charge Pumping measurement, ultra-fast traps can be characterized with high accuracy. Both electron traps and hole traps are identified in the transistor. The energy and spatial distribution for these two traps can be clearly extracted. By further comparing with ab-initio calculation, the electron traps are found to relate to dangling bonds and hole traps originate from oxygen vacancies. Electron traps can contribute up to 90% in short-term NBTI and thus could be critical for future improvement. The results are useful in understanding the reliability of sub-20nm DRAM technology.

Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25 °C to 150 °C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance–voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks.

Online NBTI-induced partially depleted (PD) SOI degradation and recovery prediction utilizing long short-term memory (LSTM)

Negative bias temperature instability (NBTI) is one of the major aging effects that account for degradation or even failure of SOI pMOSFETs. However, several modeling methods for aging prediction show limitations in some conditions. Therefore, combined with the recent development of online diagnose and prediction application, a long short-term memory (LSTM) time series data-driven model is proposed for NBTI-induced partially depleted (PD) SOI devices aging prediction, including both stress and recovery phases. The results demonstrate improved accuracy and universality while holding a reasonable time consumption.

Measurement of 64 organic thin-film transistors in an array test structure using a relay-switch board for efficient evaluation of long-term reliability

We propose an efficient array measurement test structure to measure many devices and to obtain statistical characteristics of organic thin-film-transistors (OTFT) for long-term reliability evaluation of new devices under development in laboratories and those that cannot achieve sufficient yield. We propose to adopt different devices from the device under test for the array control circuit. We implemented a separate control circuit as a dedicated relay-switch board without device consolidation. This relay-switch board can also apply voltage stress to any number of devices under test for negative bias temperature instability evaluation. The interface issue between the chip and board is resolved with a flexible flat cable and an anisotropic conductive film. The proposed measurement system successfully measured the OTFT arrays in (sweep time of source measure unit) × (number of OTFTs) period, and only requires 84 min for 64 nOTFTs (n-type OTFT) (552 points/device), which corresponds to 1.3 min/device in the experiment.

Impact of Channel Thickness on the NBTI Behaviors in the Ge-OI pMOSFETs With Al2O3/GeOx Gate Stacks

The impact of channel thickness on the negative-bias temperature instability (NBTI) behaviors has been studied for the Germanium-on-Insulator (Ge-OI) pMOSFETs. It is found that the permanent and recoverable defects are generated simultaneously during the NBTI stress of Ge-OI pMOSFETs. The lower NBTI is confirmed for the Ge-OI pMOSFETs with a thinner channel, due to the reduction of the band bending of Ev under a fixed electrical field of NBTI stress. Thus, the channel thickness scaling could be an effective method to improve the NBTI reliability for Ge-OI pMOSFETs.

Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.

An Ageing-Aware and Temperature Mapping Algorithm for Multilevel Cache Nodes

Increase in chip inactivity in the future threatens the performance of many-core systems and therefore, efficient techniques are required for continuous scaling of transistors. As of a result of this challenge, future proposed many-core system designs must consider the possibility of a 50% functioning chip per time as well maintaining performance. Fortunately, this 50% inactivity can be increased by managing the temperature of active nodes and the placement of the dark nodes to leverage a balance working chip whilst considering the lifetime of nodes. However, allocating dark nodes inefficiently can increase the temperature of the chip and increase the waiting time of applications. Consequently, due to stochastic application characteristics, a dynamic rescheduling technique is more desirable compared to fixed design mapping. In this paper, we propose an Ageing Before Temperature Electromigration-Aware, Negative Bias Temperature Instability (NBTI) & Time-dependent Dielectric Breakdown (TDDB) Neighbour Allocation (ABENA 2.0), a dynamic rescheduling management system which considers the ageing and temperature before mapping applications. ABENA also considers the location of active and dark nodes and migrate task based on the characteristics of the nodes. Our proposed algorithm employ Dynamic Voltage Frequency Scaling (DVFS) to reduce the Voltage and Frequency (VF) of the nodes. Results show that, our proposed methods improve the ageing of nodes compared to a conventional round-robin management system by 10% in temperature, and 10% ageing.

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction

With the rapid development of semiconductor technology, chip integration is getting beyond imagination. Aging has become one of the main threats to circuit reliability. In order to develop aging degradation prediction, it is critical to evaluate aging to avoid circuit failures. At present, the research on aging prediction is mainly focused at the transistor and gate levels: at transistor level, the precision is high, but the speed is low; whereas, the gate-level accuracy is not high, but the speed is very fast. In this paper, a path-level aging prediction framework based on the novel critical gate is proposed. The 10-year Negative Bias Temperature Instability (NBTI) aging delay of the critical subcircuit extracted by the novel critical gate is obtained, and the aging delay trend is learnt by using a linear regression model. Then the critical path aging delay can be obtained quickly based on the framework developed by machine learning using the linear regression model. The experimental results of ISCAS’85 and ISCAS’89 benchmark circuits based on 45-nm PTM show that the proposed framework is superior to the existing methods.